1. Field of the Invention
The present disclosure relates to a solid-state image pickup device and an image pickup device.
2. Description of Related Art
With reference to FIG. 8, a description is made below of a solid-state image pickup device (CMOS image sensor) disclosed in Unexamined Japanese Patent Publication No. 2013-168880.
FIG. 8 is a block configuration diagram of a conventional solid-state image pickup device disclosed in Unexamined Japanese Patent Publication No. 2013-168880. Solid-state image pickup device 500 disclosed in FIG. 8 includes: image pickup region 510 in which pixels are two-dimensionally arrayed in XY directions; row selection circuit 520 as a pixel driver; horizontal scanning circuit 530; timing control circuit 540; AD (Analog-Digital) converter group 550; digital-analog converter 560 as a reference signal generation circuit (ramp signal generator); amplifier circuit 570 for signal output; signal processing circuit 580; and horizontal transfer line 590. AD converter group 550 has a configuration in which AD converters, each including comparator 551, counter 552 and latch circuit 553, are arrayed for each of columns.
Each of comparators 551 compares ramp voltage Vslope with analog signals. The ramp voltage Vslope has a stepped ramp waveform output from digital-analog converter 560 through ramp signal line 555. The analog signals are output from the pixels via vertical signal lines 554 for each of row lines. Each of counters 552 counts a comparison time of comparator 551. By the above-described operations of comparators 551 and counters 552, AD converter group 550 outputs pixel signals as digital data. Such an ADC system as described above is referred to as a single-slope column-parallel ADC system.